”width”: what width are you referring to? There is nothing unusual about the execution width. There are a number of LPDDR4X channels with off-chip drivers, so you can even see how the die connects to off-die RAM. This is easy to see from the actual die photographs that have appeared on Ars (I addressed this claim in another thread and posted the picture). On die memory: there is no on die memory. I know, because I was the original designer of the reorder unit on that chip. Massive reorder buffer: UltraSparc V had that. But feel free to inform me of chips that have this style of architecture if you know of any, I’m happy to see hard facts. There are large deviations in this chip from the normal train of thought and standard processor design. How about the width compared to other silicon (and yes, I’m aware x86 struggles on width due to its instruction set baggage), the massive reorder buffer, the large number of dedicated units for processing or accelerating single tasks in parallel with the cpu, the on die memory? There are other deviations too, but then again you can easily educate yourself on that if you so wish without me spouting off about it.
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